This invention relates to apparatus for providing logic circuits as logic gates to perform logical functions in combinational and sequential digital logic systems.
The advent of large scale integration has meant that monolithic integrated circuits are becoming available with more and more digital system functions provided therein to the point that substantial portions or all of a digital system are provided on a single chip. This increase in functional density and so in circuit density in a monolithic integrated circuit has several advantages. Substantial economies are realized in reduced assembly cost, etc. Improved reliability results because fewer interconnections need to be made among the devices making up the system. There is an increase in the rapidity of operation since signals which must be transmitted in the system can be transmitted over small distances.
These advantages and others motivate the desire to increase the number of logic gates in a monolithic integrated circuit device to further increase the logic function density in such a device. Additionally, to accomplish more rapidly the logic functions to be performed to thus improve the digital system capabilities, increasing the rapidity of operation of the logic gates used in a monolithic integrated circuit device is also very desirable. Yet, both increases in circuit density and in the rapidity of circuit switching operations tend to also increase the power dissipated in the monolithic integrated circuit device and so the method chosen to reach these two goals must also provide for achieving a sufficiently low power dissipation if a viable monolithic integrated circuit device is to be realized.
Currently, the need for rapidly operating digital monolithic integrated circuit devices is met most commonly by transistor-transistor logic circuits (TTL), particularly Schottky-clamped TTL, and emitter-coupled logic (ECL). The logic gates provided in these logic families tend to use on the average more than one transistor per logic function accomplished. Use of one transistor per basic logical function would be quite desirable since the use of further transistors tends to require more space in a monolithic integrated circuit, tends to slow operation of the logic gate and tends to increase power consumption.
There have been attempts to develop new logic circuits to improve on the foregoing logic circuit families and to develop new logic families. Among these is a logic circuit shown in U.S. Pat. No. 3,769,524 to Mathews which teaches use of a NOR gate to perform logical functions. The circuitry shown in this patent teaches a somewhat simplified logic gate requiring relatively little power but still shows use of more than one transistor on the average in achieving the NOR logic function provided.